Development of semiconductor memory devices (e.g., flash memories, embedded memories, etc.) always follows the direction toward high-integration, high-capacity memory cells. In designing of flash memories, a variety of error checking and correction means are generally incorporated to ensure a high product yield of the flash memories.
Testability design techniques of memories (e.g., embedded memories) may include direct testing, embedded CPU-based testing and Built-in Self-Test (BIST).
BIST is a technique that allows a device to test itself by a relevant functional portion embedded in the circuit of the device and hence reduces its dependence on automated test equipment. Nowadays, highly integrated circuits are being widely used, which require high-speed mixed-signal test equipments for their testing. Thanks to its self-test function, use of BIST technique can reduce the need for such automated test equipments. Memory Built-in Self-Test (MBIST) is a technique incorporating one or more algorithms specially designed to test one or more types of defects in memories.
Due to high requirements on CP (Chip Probing) test time and cost, improvement efforts in memory testing have been pursuing reductions in testing time. As the time for testing of Erase, Program and Read functions cannot be shortened, a scheme in which multiple memories are tested in parallel has to be employed in order to reduce the testing time. Conventionally, testing of one memory device usually involves the use of 6, 4 or 2 signal pins, and a test instrument with 768 signal pins can therefore simultaneously handle 128, 256 or 384 memories, respectively. However, with the density, and also the number, of chip dies that can be formed on a single wafer increasing continuously, testing time required by the conventional scheme per wafer will become longer and longer, which will lead to increasing test cost.